1. Field of the Invention
The present invention generally relates to data transfers from a memory unit to a microprocessor and, more particularly, to a slave-to-arbiter signal which indicates that the end of a data tenure will be the next cycle, thus eliminating a bus turnaround cycle and increasing the effective bandwidth of the data bus by up to twenty percent.
2. Description of the Prior Art
The bus interface for modern microprocessors often specifies one or more bus cycles of dead time between data tenures to allow the previous master and slave to restore control signals and get off the system bus. This allows handoff between the previous master/slave pair and the next master/slave pair without any bus contention problems. Assuming that burst transfers require four bus cycles to complete, the dead cycle between transfers reduces maximum bus bandwidth by 20%. In cases where the same slave is involved in consecutive read data bus tenures or when the same master and slave are involved in multiple write data bus tenures, this turnaround cycle is unnecessary and reduces the potential performance of the microprocessor. A mechanism is needed to eliminate the turnaround in these cases.